Voltage-controlled oscillators are in wide use in a variety of electronic devices. In particular, in PLL (phase-locked loop) circuits and in CDR (clock and data recovery) circuits, a voltage-controlled oscillator is used within the loop and generates a desired clock signal. In case of use in the high-frequency band, often such a voltage-controlled oscillator is constituted by a resonance circuit composed of an inductor and a voltage-controllable variable capacitance element. Furthermore, in case of use in a communication device, the voltage-controlled oscillator is equipped with a plurality of variable capacitance elements so as to operate in multiple frequency bands and is so adapted that the oscillation frequency is changed by changing over among these variable capacitance elements.
FIG. 29 is a circuit diagram illustrating a typical example of a differential-type voltage-controlled oscillator that operates in multiple frequency bands. This voltage-controlled oscillator (VCO) comprises a power supply terminal 1, output terminals 2a, 2b, a loop control terminal 3, frequency-band selection terminals 41, 42, 43, cross-coupled NMOS transistors 5a, 5b, cross-coupled PMOS transistors 6a, 6b, an inductor 7, variable capacitance elements 8a, 8b, switched-capacitance bank units 13c, 13d and an output buffer 16. The portions constituted by the variable capacitance elements 8a, 8b are referred to as variable capacitance units 9a, 9b, respectively.
The NMOS transistor 5a has a source connected to ground and a drain connected to a first end of the switched-capacitance bank unit 13c, a first input end of the output buffer 16, a first end of the variable capacitance element 8a, a first end of the inductor 7 and the drain of the PMOS transistor 6a. The NMOS transistor 5b has a source connected to ground and a drain connected to a first end of the switched-capacitance bank unit 13d, a second input end of the output buffer 16, a first end of the variable capacitance element 8b, a second end of the inductor 7 and the drain of the PMOS transistor 6b. The sources of the PMOS transistors 6a, 6b are connected to the power supply terminal 1. A second end of the variable capacitance element 8a and a second end of the variable capacitance element 8b are connected in common with the loop control terminal 3.
The switched-capacitance bank unit 13c has fixed capacitance elements 181a, 182a, 183a and transistors 101a, 102a, 103a, which are switching elements, and the switched-capacitance bank unit 13d has fixed capacitance elements 181b, 182b, 183b and transistors 101b, 102b, 103b, which are switching elements. First ends of respective ones of the transistors 101a, 102a, 103a, 101b, 102b, 103b are connected to ground. Second ends of respective ones of the transistors 101a (i=1, 2, 3) constitute the first end of the switched-capacitance bank unit 13c via respective ones of the fixed capacitance elements 18ia. Second ends of respective ones of the transistors 10ib (i=1, 2, 3) constitute the first end of the switched-capacitance bank unit 13d via respective ones of the fixed capacitance elements 18ib. Control ends of the transistors 10ia (i=1, 2, 3) and control ends of the transistors 10ib (i=1, 2, 3) are connected to respective ones of the frequency-band selection terminals 4i (i=1, 2, 3).
The output buffer 16 has output transistors 14a, 14b and output resistors 15a, 15b. The output transistor 14a has a source connected to ground, a gate serving as a first input terminal of the output buffer 16 and a drain connected to the output terminal 2b and to the power supply terminal 1 via the output resistor 15a. The output transistor 14b has a source connected to ground, a gate serving as a second input terminal of the output buffer 16 and a drain connected to the output terminal 2a and to the power supply terminal 1 via the output resistor 15b. 
The fixed capacitance elements 181a, 182a, 183a, 181b, 182b, 183b usually are implemented by fixed capacitors such as MIM (Metal Insulator Metal) capacitors. With regard to capacitance values C1, C2, C3, C1, C2, C3 of the fixed capacitance elements 181a, 182a, 183a, 181b, 182b, 183b, respectively, the resistance values C1, C2, C3 usually are set to values that differ from one another. Band setting signals VSW1, VSW2, VSW3 that are input to the frequency-band selection terminals 41, 42, 43, respectively, are controlled as high-level, low-level binary values, thereby changing the capacitance values in the switched-capacitance bank units 13c, 13d and, hence, changing over the oscillation frequency of the voltage-controlled oscillator. Although this example illustrates a case in which the number of bits constituting the respective band selection signals is three, the number of bits is set to any number as required.
The operation of the VCO set forth above will now be described. The cross-coupled portion formed by the NMOS transistors 5a, 5b and the cross-coupled portion formed by the PMOS transistors 6a, 6b produce negative resistance. Owing to the fact that this negative resistance compensates for loss, which are generated in other portions of the circuit, at the oscillation frequency, a sustained oscillatory operation is realized.
Oscillation frequency f is expressed approximately by the following equation as a function of control voltage VCNT applied to the loop control terminal 3:
                              f          ⁡                      (                          v              CNT                        )                          =                              1                          2              ⁢              π                                ⁢                      1                                                            (                                      L                    2                                    )                                ⁡                                  [                                                            C                      f                                        +                                                                  C                        v                                            ⁡                                              (                                                  v                          CNT                                                )                                                              +                                          C                      SW                                                        ]                                                                                        (        1        )            A frequency f(VCNT0) that prevails when the control voltage VCNT is a center voltage VCNT0 is referred to as the “center frequency”. Here Cf represents the contribution of a parasitic capacitance component of portions other than variable capacitance units 9a, 9b of the NMOS transistors 5a, 5b and PMOS transistors 6a, 6b, etc. Further, CV represents the capacitance of the variable capacitance units 9a, 9b, and CSW represents the capacitance of the switched-capacitance bank units 13c, 13d. The capacitance CSW can be set to eight values of from 0 to (C1+C2+C3) by the input signals to the frequency-band selection terminals 41, 42, 43. In order to simplify the description, the capacitance of the switching transistors 101a, 102a, 103a, 101b, 102b, 103b is ignored. Further, since the circuitry is differential circuitry, Cf, Cv, CSW represent the contributions only on one side. In addition, L is the inductance of the inductor 7.
The center frequency can be varied discretely by changing the value of CSW, thereby making multiband operation possible. The VCO gain in this case is as follows:
                                                                                          ∂                  f                                                  ∂                                      v                    CNT                                                              ⁢                              |                                                      v                    CNT                                    =                                      v                    0                                                                        =                                                  -                                     ⁢                                  ⁢                                                                                                                                                          ⁢                                                                  ⁢                                  1                                      4                    ⁢                    π                    ⁢                                                                  L                        2                                                                                            ⁢                                                                  ⁢                                  1                                                            [                                                                        C                          f                                                +                                                                              C                            v                                                    ⁢                                                      (                                                                                          v                                CNT                                                            =                                                              v                                0                                                                                      )                                                                          +                                                  C                          SW                                                                    ]                                                              3                      2                                                                      ⁢                                                                  ⁢                                                      ∂                                          C                      v                                                                            ∂                                          v                      CNT                                                                                  ⁢                                                          ⁢                              |                                                      v                    CNT                                    =                                      v                    0                                                                                                          (        2        )            
The gain of the conventional multiband VCO shown in FIG. 29 is given by Equation (2). In a case where the center frequency is varied to perform multiband operation by setting the band selection signals VSW1, VSW2, VSW3 of the frequency-band selection terminals 41, 42, 43, respectively, only CSW within the square brackets [ ] of the denominator changes and the other elements remain unchanged among the elements that constitute the VCO gain. Accordingly, a change in the center frequency (a band selection) is accompanied by a fluctuation in the gain of the VCO. In a case where CSW is increased and the center frequency is lowered in accordance with Equation (1), VCO gain declines in Equation (2). Conversely, in a case where CSW is decreased and the center frequency is raised in accordance with Equation (1), VCO gain increases in Equation (2). Accordingly, the relationship between center frequency and VCO gain is as shown in FIG. 30.
VCO gain is a parameter that has strong influence upon the loop characteristics of the PLL and CDR circuit. If VCO gain fluctuates in dependence upon the center frequency, the characteristic of the PLL formed using this VCO will fluctuate in dependence upon the operating frequency, and the characteristic of the CDR circuit will fluctuate in dependence upon the operating speed. This makes it difficult to achieve stable operation in the PLL which operates in multiple frequency bands and in the CDR circuit which operates at multiple bit rates.
A voltage-controlled oscillator with little frequency conversion gain (VCO gain) fluctuation is disclosed in Patent Document 1. This voltage-controlled oscillator has a configuration using a parallel circuit composed of a first variable capacitance element and a first switched-capacitance bank unit, and a series circuit composed of a second variable capacitance element and a second switched-capacitance bank unit.
Patent Document 2 discloses a PLL circuit arrangement in which a voltage adjusting circuit for performing a voltage conversion with respect to an output signal of a charge pump circuit is inserted into a PLL loop and the voltage conversion coefficients of the voltage adjusting circuit are varied in accordance with a band selection signal of a VCO.
Patent Document 3 discloses a voltage-controlled oscillator that includes a resonance circuit having an inductor and a plurality of variable capacitors the capacitance values whereof can be varied by a control voltage, the oscillator further including a variable-capacitor selecting unit, the selecting operation of which is controlled by a variable-capacitor setting signal, for selecting a variable capacitor, which supplies control voltage, from among the plurality of variable capacitors, wherein each of the plurality of variable capacitors comprises two variable capacitors of different polarities in terms of a change in capacitance thereof in response to control voltage.
The voltage-controlled oscillator of Patent Document 3 will be described in detail. FIG. 31 is a circuit diagram representing in detail a resonance circuit in the voltage-controlled oscillator of Patent Document 3. In order to simplify the drawing, only the resonance circuit relating to one set of variable capacitors is extracted and illustrated. The resonance circuit has an inductor L and variable capacitors C101, C102 the capacitance values of which are can be varied by a control voltage VCONT. The variable capacitors C101, C102 are selectively operated by a variable-capacitor setting signal. Whether the variable capacitors C101, C102 are connected at first ends thereof to a power supply VDD or are supplied with the control voltage VCONT is selected by operatively associated switching elements S101, S102. It should be noted that the variable capacitors C101, C102 exhibit different polarities in terms of the change in capacitance thereof in response to the control voltage VCONT.
[Patent Document 1]
Japanese Patent Kokai Publication No. JP2007-267353A
[Patent Document 2]
Japanese Patent Kokai Publication No. JP2005-311690A
[Patent Document 3]
Japanese Patent Kokai Publication No. JP2004-254162A